GLOBALFOUNDRIES Pipeline-TBD (MTS Design Enablement (SoC design, PPA(Power Performance Area benchmarking) in United States
Implementation of digital SoC building blocks from RTL synthesis to GDS sign-off including timing, power, and area optimization
Benchmarking the power, performance and area (PPA) of new GLOBALFOUNDRIES technologies with respect to specific market segments
Invent new idea or technique to improve PPA
Close collaborating with design methodology, PDK development, and physical IP development teams as well as EDA vendors
Ability to work independently in an international team, to drive project definition, execution, and delivery is highly desirable.
Very good understanding of process technology, digital design, and digital implementation and PPA analysis.
Deep hands-on experience with SoC/digital implementation methodology, tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS) including RTL synthesis, place and route, parasitic extraction, static timing, power and DFM /DFT (Synopsys, Cadence, Apache) and physical verification (Mentor, Synopsys, or Cadence) for advanced technologies like 28nm through 7nm.
Strong knowledge in design closure preferably gained by work on at least one full chip tape-out, including block closure for timing and performing logical and physical ECO.
At least 6 years of relevant work experience and an M.S. or Ph.D. degree in electrical or computer engineering or related field.
Strong communication skills within a global team and the ability to define and execute projects independently.
Good EDA tool scripting and automation experience (TCL, Perl, Make).
High performance, Low power design techniques and UPF (IEEE 1801)
Understand system and microarchitecture of SoC
Experience in chip tape-out and chip bring-up
Digital circuit design knowledge or experiment will be a plus
Title: Pipeline-TBD (MTS Design Enablement (SoC design, PPA(Power Performance Area benchmarking)
Requisition ID: 17006628