Rambus Principal Engineer - Circuit Design Engineering in Bangalore, India

Responsibilities

  • Have full ownership of IP, its major blocks or sub blocks

  • Support marketing on presales activities technically

  • Be the interface to the customer in technical interactions, feasibility analysis, design reviews, parameter estimations (like Power/Area etc.)

  • Pair with similar domain experts across other geographical locations on core technical initiatives

  • Define the architecture and uArchitecture of the IP’s and its sub functions

  • Understand and disseminate applicable standards and its relevance in a given project to the team

  • Responsible to develop and design the high speed circuit blocks used in Rambus

  • Design, simulate and characterize high performance CMOS data communication circuits (drivers, receive equalizers, PLLs, high speed samplers, clock recovery circuits).

  • Responsible for Receiver, transmitter or PLL level designs and top level ownership.

  • The designer will be responsible for all aspects of designs such as schematic capture, layout review, simulation & analysis of critical electrical and timing parameters, documentation and silicon bring-up.

  • Will be responsible to work with the system engineering team for Silicon bring up and Characterization.

  • Mentoring of junior designers where applicable.

Qualifications

  • 12+yrs of relevant experience in Analog Circuit Design with MS/M-Tech degree in electronics/VLSI and In exceptional cases B.E/B-Tech in electronics engineering.

  • The candidate should have prior experience of high speed custom circuit design. The senior position requires demonstrated ability to have worked in these domains and a sound understanding of the standards, protocols, practical aspects of circuit design in DSM process nodes ( 28nm, 16nm,14nm) are very desirable.

  • Strong fundamental knowledge is essential. Sound knowledge of basic building blocks (Ex: bias generation, on-chip regulation, on-chip impedance circuits and PLL) is highly desirable.

  • Experience in designing memory interfaces such as DDR/3/4 and LP3/4 or serial links such as USB/XAUI/, CEI6/ LVDS /PCIE//SATA and Display Port etc.)

  • Experience working in leading R&D and future technology development projects is desirable.

  • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.

Job ID2016-5065

CategoryEngineering