GLOBALFOUNDRIES PMTS Design Enablement - Digital Methodology Engineer in Santa Clara, California
This position reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of Technology nodes. Your role is focused on the development of Digital design enablement collateral to help GLOBALFOUNDRIES customers adopt the most advanced silicon technologies (14/10nm/7nm).
Essential Responsibilities: ● RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification ● Will be closely collaborating with EDA vendors, foundry technologists, PDK and design teams to define, implement, customize, and qualify digital design flows ● Develop low power flow techniques using UPF and other industry standard solutions. ● Benchmarking the power, performance and area (PPA) of new GLOBALFOUNDRIES technologies ● The ability to work independently in an international team, to drive project definition, execution, and delivery is highly desirable. ● Perform all activities and responsibilities in safe and responsible manner and support all Environmental, Health, Safety, Security requirements and programs
Required Qualifications ● 10 years of relevant work experience with BS degree in electrical or computer engineering or related field.
Preferred Qualifications ● MS or Ph.D. degree in electrical or computer engineering or related field. ● 12 years hands-on experience using version control software like Perforce and Low power design techniques and UPF (IEEE 1801) ● Strong communication skills within a global team and the ability to define and execute projects independently. ● Strong knowledge of process technology, digital design, and digital implementation and analysis EDA tools and flows. ● Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS, or Mentor Nitro) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence) and/or physical verification (Mentor, Synopsys, or Cadence) for advanced technologies like 16/14/10/7nm. ● Strong knowledge in design closure preferably gained by work on at least one full chip/block closure for timing and performing logical and physical ECO. ● Stron understanding of liberty (.lib) formats including variation formats like AOCV/LVF ● Strong EDA tool scripting and automation experience (TCL, Perl, make).
If you need a reasonable accommodation for any part of the employment process, please contact us by email email@example.com let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer of employment with GLOBALFOUNDRIES is conditioned upon the successful completion of a background check and drug screen, as applicable and subject to applicable laws and regulations.
GLOBALFOUNDRIES is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, or protected Veteran status.
Organization: *DESIGN INFRASTRUCTURE-00083354
Title: PMTS Design Enablement - Digital Methodology Engineer
Location: North America Region-California-Santa Clara-US,CA,Santa Clara
Requisition ID: 16002148